I would like to to generate a hardware timed TTL signal on Ni PCI-6289 and manually configure the sample rate to some lower value as 1k or 10k. I'm using the python API for NI-DAQmx. When I run a simple demo like:
from nidaqmx.constants import LineGrouping
from nidaqmx.stream_writers import DigitalSingleChannelWriter
import numpy as np
delay = 3*(10**3)
a = np.empty(delay, dtype="uint32")
for i in range(delay):
a[i] = 0
a[delay-1] = 1
with nidaqmx.Task() as task:
task.do_channels.add_do_chan("Dev1/port0/line0:0", line_grouping=LineGrouping.CHAN_PER_LINE)
task.timing.cfg_samp_clk_timing(1000)
writer = DigitalSingleChannelWriter(task.out_stream, auto_start=True)
writer.write_many_sample_port_uint32(a)
(environment Python 3.7 with PyCharm, nidaqmx 18.5, Windows10)
It will raise an error:
Traceback (most recent call last):
File "<input>", line 1, in <module>
File "C:\Program Files\JetBrains\PyCharm 2018.2.4\helpers\pydev\_pydev_bundle\pydev_umd.py", line 197, in runfile
pydev_imports.execfile(filename, global_vars, local_vars) # execute the script
File "C:\Program Files\JetBrains\PyCharm 2018.2.4\helpers\pydev\_pydev_imps\_pydev_execfile.py", line 18, in execfile
exec(compile(contents+"\n", file, 'exec'), glob, loc)
File "C:/Users/LYCLab/PycharmProjects/Labctl/di_test.py", line 15, in <module>
writer.write_many_sample_port_uint32(a)
File "C:\Users\LYCLab\PycharmProjects\Labctl\venv\lib\site-packages\nidaqmx\stream_writers.py", line 930, in write_many_sample_port_uint32
self._verify_array(data, False, True)
File "C:\Users\LYCLab\PycharmProjects\Labctl\venv\lib\site-packages\nidaqmx\stream_writers.py", line 113, in _verify_array
channels_to_write = self._task.channels
File "C:\Users\LYCLab\PycharmProjects\Labctl\venv\lib\site-packages\nidaqmx\task.py", line 168, in channels
self._handle, flatten_channel_string(self.channel_names))
File "C:\Users\LYCLab\PycharmProjects\Labctl\venv\lib\site-packages\nidaqmx\_task_modules\channels\channel.py", line 118, in _factory
check_for_error(error_code)
File "C:\Users\LYCLab\PycharmProjects\Labctl\venv\lib\site-packages\nidaqmx\errors.py", line 127, in check_for_error
raise DaqError(error_buffer.value.decode("utf-8"), error_code)
nidaqmx.errors.DaqError: External sample clock source must be specified for this application.
Task Name: _unnamedTask<0>
Status Code: -200303
This script works without the cfg_samp_clk_timing() function (set delay to 10**7). but according to oscilloscope the real delay is only 0.3s.
I have tried some alternative methods, such as specified the source as "Dev1/10MHzRefClock". However, it will raise another error which suggests either use OnBoardClock or change the sample rate according to the clock timebase.