Hello,
I am seeking for some suggestions from those working with degital delay generators.
We have a TTL trigger pulse train in which pulses are not equidistant in time (seperation between two pulses is not the same, it can be few ns to few microsecond), however, on average, the rate would be <2MHz. The pulses are 10-20ns width and 2.5V amplitude. From this, we want to generate 3-4 trigger pulse trains, which would be delayed with respect to the initial (input) pulse train by some arbitrary values (ns to few microsecond). However, the point is, we also want some trigger pulse trains in which only even number of triggers (or odd triggers) could be present. So in other words, we want to program the delay generator in such a way that one of the outputs could have only even or odd trigger pulses of the initial trigger pulse.
We first tried to look for available delay generator boxes and PCI delay generators. The problem is that they have insertion delay of typically 50ns or more. So in other words, the output triggers would be delayed from the initial trigger pulse not less than 50ns. Other, If we program them with labview, It seems the output response would be after few ms. These are quite large delays for us.
One such delay box manufecturing company suggested us to use FPGA based delay generators, as they say that these devices are having low insertion delays and quite fast programmable response. I looked in NI website for insertion delay and other parameters, but could not find these values. Pl. suggest whether FPGA based delay generators have low insertion time (<10-30ns) and if we program them, the output could be generated within ns response time?? As I am new with such devices, I would sppreciate if anyone could suggest about the possibilities to generated the delay sequences (even only or odd only triggers) using FPGA devices.
Thank you