Limitation in number of DMA FIFOs for multip-up parallel comm with FPGA

Hi

I am using 7820R in a project to send data back and forth between host and target. So far ,my setup was 4 and in target I have 4 SPI engines that they can run fully in parallel

They all had their own DIO for SPI and their own DMA FIFO for read and write . I have 4 DMA write and 4 DMA read to send data between host/target. Now I want to expand this code to 16UP

I don't have any limitation in number of DIOs but now I need 16 FIFO read and 16 FIFO write and 7820R only has 16 FIFOs

Is there any design that I can just use 1 FIFO for read/ 1 FIFO for write and I can still keep the fully parallel model so the SPI engines can run fully in parallel?