Dear NIDev Community,
I'm currently looking into implementing an application for digital pattern testing of a high channel count device.
The example that closely matches my application is the memory test reference design from NI web (did_mem_test.zip).
Memory Test Reference Design
http://www.ni.com/white-paper/7966/en/
In the reference design, a single HSDIO device is used to generate a write and compare pattern and the errors analyzed. In my application, I will need to distribute the digital signals across several HSDIO modules since each module has limited digital lines.
Module 1 and 2: Data lines
Module 3: Address lines
Module 4: Clock, chip enable, etc.
I would need your kind help to understand how I should implement the reference design to fit an application that spans across several modules. If you are able to give me a simple example code I will be able to move ahead from there.
My intention is to use HWS waveform patterns created using the Digital Waveform Editor and if possible to use NI-TCLK to synchronize the devices. I have attached a VI that I had modified from an example program but I'm not sure if I'm implementing it correctly. I've also zipped the reference design code too.
I'm using four PXI-6551 devices and LabVIEW 2013.
Thank you for your kind help. 
Cheers!
Sanka