I'm using a USB-6363 interface with two SCB-68 terminal boxes. Each box is connected using a 2-meter SHC68-68-EPM cable to the 6363.
I am using Port 0 to generate digital waveforms using an 8 MHz clock. The FIFO buffer appears to be able to handle the data rate, but the quality of the digital signals at the terminal boxes is an issue. Specifically there are overshoot, undershoot, ringing, and crosstalk between channels. This is causing false triggering on the device under test. See attached scope plot. The measurements were made directly at the terminal box without the DUT connected. The yellow trace is on P0.0, and the green trace is P0.3. The crosstalk is reduced on channels located on the other connector, but it is still there. I am using 20 digital outputs from the 6363, so I can only sepatarate certain groups of signals to each terminal box.
The device I am testing nominally runs at 1V Vdd, so I am using NXP NVT20xx series level shifters to bring the logic-high levels from 5V down to 1V. These level shifters clamp any high voltages to about Vdd + 0.25V, but anything lower gets passed through almost verbatim. This means that any extraneous signals centered around logic-low are problematic because it only takes a few 100 mV to cause false triggering on the DUT.
It is my suspicion that the 2m length of the cables is the main cause of my problems. I know that this same cable is available in 0.5m lengths. I have told my supervisor/professor that we may have to order shorter cables, but I want to see if it’s possible to mitigate the issues with additional circuitry before purchasing.
I have searched through knowledgebase articles and forum posts, but most of what I found concern matching impedances on devices designed for 50 ohm loads. It is my understanding that the 6363 is not designed for matched networks, but is there a recommended termination or filter circuit that can significantly reduce the unwanted anomalies? Ideally I’d like to avoid sacrificing rise/fall times too much. Also attenuation of the signals needs to be minimized since there are times that the Vdd will be at 3V, i.e. the logic-high input signals need to be at or above Vdd in order for the level shifters to work properly.
I have tried adding load resistance (min. 220 ohms to limit current to less than 24mA), and this significantly reduces the ringing. However, it might be problematic dealing with the ground return paths for that much current on 20 channels. I have also tried RC low-pass filtering, but sufficiently reducing the ringing leads to long rise/fall times.
If it turns out that ordering shorter cables is a better solution, will the 0.5m cables be short enough to reduce the anomalies sufficiently? Will I still need termination/filtering on each channel?