Hi, I have developed a program for demodulation of RF data stream in FPGA 7999 interfaced with NI tranceiver 5791.Data gets demodulated and than stored to FIFO as required. After acquiring RF data stream it gets demodulated IN FPGA.Recovered data is than output from NI 5791 transceiver Digital IO port. I have question regarding data which is getting out from 5791 is in pulse like form.BUt I require data to be of continuous type rather than pulse form. My second query is that I also want to generate clock with the demodulated data.Right now I have mapped output enable pulse at output but my objective is to output a proper clock with akllmost 50% duty cycle with continuos demodulated data. VI is attached kindly look and guide accordingly.Thanks sample project is also attached
↧