I have a project with 9411 differential DIO card installed on a 9033 cRIO. We are measuring pulse widths of a digital signal.
This means we measure the number of clock ticks in our 9033's FPGA between one rising edge and the next. The FPGA in this cRIO has a 40 MHz clock and so a clock tick is 25e-9 seconds. So far so good.
Except the 9411 has a published clock rate of 2 MHz.
So what I want to know is how these two clocks interact to affect my measurement. (The period of the digital signal.)
If the 9411's clock is synchronized to the 9033, then I would expect that my edges would show up to the FPGA only in multiples of 500e-9 seconds regardless of when they occur.
If they are not synchronized, then I would expect the period of several cycles to vary a little but that an average would show some multiple of 500e-9 seconds.
Or possibly some third thing that I haven't even guessed at.
Unfortunately I don't have access to the system right now or I would run some tests and figure which of these 3 it is. So I am turing to the wisdom of the forums.
In short, how do the two clocks interact when I am making a pulse width measurement? How does this interaction affect my pulse width measurement?
FWIW, our high end frequency is 81920 Hz.
Thanks!