Digital voltage range limit (less V)

Hi

My first post here.

In the Datasheet and in the examples i was not able to find a solution for my problem:

- output voltage digital 0-5V <-> input FPGA (3V3)

because i am communicating with a FPGA i have a problem with the output voltage of the USB-6221 to the FPGA. 

Is it anywhere possible to change the digital output voltage range 0-5V? The other way is no problem, because the USB6221 accept 2.4V as an high (3V3 output of FPGA)

I am looking for an solution per CVI property to limitate the voltage range

-> the last solution will be a very simple voltage divider. But i need this for more than 2 lines.

Thanks for your help!