Dear NI,
I need your input to choose the CDAQ Hardware/Any NI DAQ, to measure 40V/1A digital output of our Custom made product. So please provide us the feedback to speed up our Hardware procurement to measure the mentioned digital signal output
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40V/1A Digital ouput measurement
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read AI and DI simultaneously
Hello,
I want to read AI and DI simultaneously(of course there should be some gap during sampling time and read time?)
I'm using USB-6361, NIMAX 19.6, python 3.7.6, windows 10.
I don't mind if you give me any idea not only for python but also any other text based method.
I wanna read 2 channels of AI (1MS/s/ch) and 2 channels of DI all together.
I used function generator to make sine wave(3.2V amplitude, 1kHz) and connected it to ai0. And connected sync to PFI0.
If I set timeout of ReadDigitalLines to 0, it seems it lost a lot of DI data (or maybe clock freq. is too high? I'm not sure of it. Actually I couldn't found any information about how DI works.) Like the plot below. (orange line is DI. I drew only 1 AI chan and 1 DI chan.)
If I set timeout of ReadDigitalLines to -1, it seems it reads DI data too much. (or maybe clock freq. is too low? Again, I'm not sure of it.) Like the plot below. It also breaks after it reads data only once.
And this is zoom-in plot.
Please let me know if somebody has any idea.
My code is as below.
nidaq.DAQmxCreateAIVoltageChan(AItaskHandle,b"Dev%d/ai0,Dev%d/ai2" %(num,num),"",DAQmx_Val_Diff,float64(-5.0),float64(5.0),DAQmx_Val_Volts,None)
nidaq.DAQmxCreateDIChan(DItaskHandle,b"Dev%d/PFI0,Dev%d/PFI1" %(num,num),"",DAQmx_Val_ChanPerLine)
nidaq.DAQmxCfgSampClkTiming(AItaskHandle,"",float64(sampleRate),DAQmx_Val_Rising,DAQmx_Val_ContSamps,uInt64(1000000))
nidaq.DAQmxStartTask( DItaskHandle )
nidaq.DAQmxStartTask( AItaskHandle )
while True:
readAI = uInt32()
readDI = uInt32()
bytesPerSamps = uInt32()
nidaq.DAQmxReadAnalogF64(AItaskHandle,samples_per_chan,float64(-1),DAQmx_Val_GroupByScanNumber,AIdata.ctypes.data,Length,ctypes.byref(readAI),None)
nidaq.DAQmxReadDigitalLines(DItaskHandle,samples_per_chan,float64(0),DAQmx_Val_GroupByScanNumber,DIdata.ctypes.data,Length,ctypes.byref(readDI),ctypes.byref(bytesPerSamps),None)
Someone suggested me to set sample clock for DI like this: nidaq.DAQmxCfgSampClkTiming(DItaskHandle,"Dev%d/ai/SampleClock" %num,float64(sampleRate),DAQmx_Val_Rising,DAQmx_Val_ContSamps,uInt64(1000000))
But it doesn't read DI in this case. (I heard that it works for M series PCI board. Mine is X series, USB.)
But it doesn't read DI in this case. (I heard that it works for M series PCI board. Mine is X series, USB.)
Thank you in advance!
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Exported/imported clock signal from/to NI 658x
Hello,
We have a PXI system in my organization (PXIe-1062Q and PXIe-8840) that we are looking into upgrading with a PXIe FlexRIO and a 658x modules.
The idea is to control several Integrated Circuits (ICs) from the PXI, among others, high speed ADCs, such as AD9649 or AD9245.
The AD9245 needs a CLK single-ended input signal, of up to 80 MHz with low jitter (in the order of units of ps rms). Is it possible to generate this kind of signals with a PXIe FlexRIO module?
On the other hand, a device such as the AD9649, provides a single ended data clock output signal (DCO), to synchronise data acquisition. I have seen approaches where this signal is configured as a digital input to the FPGA (like in this post), which is sampled to look for edges. I was wondering, would it be possible to import this DCO signal as a clock signal within the FPGA (as explained here) and then use this clock as a SCTL clock? What would be the specifications of this signal (in terms of duty cycle, jitter, etc.) from the FlexROP/658x module point of view?
Best regards,
Isacar.
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cDAQ-9181 Digital Output is Slow
Hello,
I am using c Series 9375 digital IO module on cDAQ-9181 ethernet chassis.
The software used is VBAI 2018. Global virtual channels are created under MAX in order to be able to use the device on VBAI.
This device generates outputs much slower than I expected. Attached the screenshot of the benchmark, you can see the time it takes to write an output LOW command is 68ms in average.
In datasheet, it is written that device should generate signal in less than 1ms. I can understand a couple of ms difference or maybe around 10ms because of the software/platform, but it is weird that this operation took 68ms.
Computer(Win10 x64) has core i7 CPU, and I can get much faster results on same computer even with device like USB-6501.
Is this normal behavior for cDAQ on VBAI?
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NIMAX simulating a device for Non NI application
I am currently developing a .Net application for my company that required the use of USB6525 Dig I/O.
I am awaiting delivery of NEw USB6525s from NI so thought I could simulate them in NIMAX for the .Net App to be able to use whilst being set up.
This does not seem to be possible as I am unable to toggle inputs or display outputs through NIMAX for the .Net App to be able to see.
As soon as I run a task or start the "test Panels" of a simulated device the .Net App is locked out of the device by NIMAX.
Any ideas how to allow the .Net App to access the simulated device and allow I/O simulation via NIMAX ?
( NIDAQMX 19.6 & associated NIMAX)
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USB-6501 OEM
I am trying to buy USB-6501 OEM modules, but cannot find them listed on the website. The User Guide is available but it does not show up as hardware option when trying to add it to the cart. What is the correct NI part number to order or am I missing something?
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HSDIO 6541 aquisition speed
I am trying to read data packets that are coming at a rate of 1KHz. I have 4 data lines, a 32khz clock, and a data start line at 1KHz. I am read all 6 lines so I can process the data properly. I am using an onboard clock at 1Mhz and reading 210 data points. I am triggering on a data start line using PFI1 and reading 210us worth of data. The HSDIO read is taking 2ms to execute so I am missing half of the data. Is that any way to speed up the data read so that I don't miss any of the data start triggers.
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Max number of samples captured per pin on PXIe 6570
What is the max capture memory for each 6570 digital pin, given 32 pins on card?
How many points max can be captured on a given digital pin in a pattern before it runs out of memory?
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NI-6583 with PXIe-7976r error code -63150
I get the following error when executing my VI:
Error -63150 occurred at niLvFpga_Open_PXIe-7965R.vi
Possible reason(s):
NI-RIO: (Hex 0xFFFF0952) An unspecified hardware failure has occurred. The operation could not be completed.
The error occurred when I used the NI-6583 digital I/O module with PXIe-7976R to run the signal generation example. I changed the slot 7976R used and confirmed the connection between NI-6583, but the error still existed. The module worked fine days ago, but today it went bad. Is there any hardware problem with NI - 7976R ?
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Shock/Vibration rating NI USB-6002
What vibration environment conditions are tested and certified for the NI USB-6002?
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cRIO-9030 calibration for new sensor
Hello
We bought a new force sensor and want to replace old one on Tensile machine. The problem is that sensors with out load always shows +300kg. As I correctly understand we need to calibrate an amplifier cRIO-9030. Please, suggest - how to do it? Unfortunately have no experience in this issue.
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Using PXIe-6571 as a I2C SLAVE
Hi,
I'm a new guy in this field of work, and there is much questions to ask, but let me start with a simple one. I saw an example of 6571 as an I2C MASTER so I was wandering if such a device could behave also as a bus SLAVE.
I'd like to test some parameters on a MCU bus MASTER via Digital Pattern Editor or LabView.
Please advise the possible work flow direction regarding the use of PXIe-6571.
Many thanks!
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PCI-6536
Hi,
I have PCI-6536 and PCI-6536b. Can anyone please tell me how can i use both in one computer in scanning machine and how to install driver separately for both.
Thanks
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657x Digital How does digipat vector length loaded into card count against 128M Vector LVM?
Hi All,
I pre-load about 30 digipat patterns to my 657x. Each pattern is about 6M vectors long. This would seem to be 30*6 = 180M Vectors loaded to card at start of test. But, 657x spec says LVM is 128M Vectors. I'm confused why I get no errors and the patterns run successfully.
Is there any documentation on what 'counts' as a vector against the 128M LVM?
Thanks
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工作站数据采集缓存
我们采用NI 5781采集数据，运行其中的NI 5781-Getting start例程，里面可以设置数据长短，发现最大只能设置65535，而采样频率为100MHz，得到的数据是不连续的。当设置过大时显示buffer overflow ，请问是否有解决办法？
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Why the pulse width and pattern gets changes for each level while converting a signal from analogue to digital using ADC VI.
Task:
i am trying to multiplex two signals using time division multiplexing, for that purpose
step 1) i took two analogue signals using simulate signal VI and displayed the same using mixed signal VI.
step 2) converted both the signals into digital using Analogue to Digital converter VI and displayed the same using mixed signal VI.
step 3) using case structure as commutator switch to select between the signals to transfer/ display as TDM channel.
Problems :
1) in step 2 display, why the pulse width and pattern gets changes for each level while converting a signal from analogue to digital using ADC VI. the pulse width and pattern is changing by changing by changing any of the three: a) amplitude of signals, b) frequency of signals and, c) by changing the slot duration or frequency/ select time(true/ false time) of case structure i.e. commutator switch frequency.
2) unable to concatenate the data streams and view the data stream in TDM channel for two or more time slots.
Please look for the waveform and pulse pattern in screenshots.
please provide the solutions and comment your views, as I am eagerly waiting to know the reason behind this.
i will be thankful to members for sharing there knowledge and solutions.
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6571 encounter error -1074102162 during initial
Hi ,
In my test case, I use a SMU and 6571. We will occasionally have error from SMU and then our test sequence will skip the close session step of 6571. When we try to run the test sequence again, we will encounter this error -1074102162 in 6571 initial every time.
And when this error happen , windows will turn to blue screen 10 sec after error happen.
only power down first and power on again can fix this issue.
Not sure what happen.
We're using digial pattern driver 19.0.1
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PXI-6289 SPI Protocol, Simultaneous Generation & Acquisition
Good day all,
I am trying to implement the SPI protocol in a PXI-6289. I am generating the SPI waveform with the SPI Digital Waveform library, then outputting through regular I/O (CS,SCLK, MOSI) as shown bellow.
VI: Attached below.
Note: I am aware of the thin clock cycle at the start of the transmission, but that is probably tied to my SPI settings. Not an Issue.
What I have not quite figured out is how to read/sample digital inputs (MISO) during the exact same time as my other signals are being outputted. This is to emulate the full duplex communication.
Ideally, I would test this by tying MOSI and MISO together and see how off these are on the scope.
I have tried a couple of options with Triggers, Timing blocks and Events, but these seems to be restricted due to the hardware I'm using. Since this PXI 6289 is all I can use for now, I am asking for any suggestion of what I could do in this scenario.
I appreciate your responses. Thank you,
Sebastian B.
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2x 68-pin VHDCI to 2x 50-pin IDC
Legacy configuration = PCI-6025E (100-pin) connected with R100-50-50 cable to custom motherboard (2x 50-pin)
New configuration = PCIe-6323 (2x 68-pin) connected with ??? cable to custom motherboard (2x 50-pin)
What possible option is available to replace the "???" cable above?
So far...Found R68-50 appears would adapt Connector 0. However, not Connector 1...(?)...has a different pinout.
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open drain and push pull mode on sbrio 9628
Hi,
Related with covid-19 , I am in the process of developing a resuscitation ventilator, I use a flow sensor which communicate with the i2c protocol, I followed all the steps mentioned in the datasheet but my problem is that the sensor always responds with zeros even by varying the flow, i asked the manufacturer of this sensor, he told me that the sensor only works in open drain mode and not in push pull mode, I use the sbrio 9628 can any one help me to configure DIOs on open drain mode? if it is possible .
thank you and best regards .
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