We have a research study about denoising biomedical signals through hardware implementation using FPGA. A model-based design of the denoising algorithm in Simulink was converted into Verilog HDL code using HDL Coder in Simulink. The Verilog HDL Code was synthesized and being programmed using FPGA Cyclone V DE10-Standard Board. The input and output pins of the code consists of 16 pins. In the FPGA, we utilized the GPIO or General Purpose Input and Output Pins to program the Verilog HDL code using Pin Planner in Intel Quartus II. We want to test whether the programmed FPGA in denoising signal is working. The test setup is the 16 bit signal from the Simulink will send its data using the NI DAQ USB 6353 to its digital output. The digital output of NI DAQ is connected to the 16 bit inputs assigned in the FPGA. Lastly, the digital output pins of the FPGA is connected to the input pins of the NI DAQ so that the results of the FPGA would reflect in the simulation in Simulink. We found that the FPGA has 3.3 TTL output logic in the digital I/O pins of the FPGA. And upon simulation, we cannot get the expected results that the input biomedical signals should be denoised using FPGA.
Is it right that the Digital I/O Logic level on NI DAQ USB 6353 is 5V TTL? If yes, is it right to connect a 3.3 V TTL logic of the FPGA into a 5V TTL of the NI DAQ? Is it required that the TTL logic of both device should be matched in order to yield an expected results? If yes, what steps should we in order to change the TTL voltage level of NI DAQ USB 6353 into 3.3V TTL?
You can email me at penuliarcarl07@gmail.com to have longer conversation with regards to our problem. Thank you very much