FPGA SPI share clock

Hi,

I would like to create an Interface which can write SPI (Digital IO) but read different format (Analogue port), there is a problem as I need to use the same clock.

I have been looking at "http://www.ni.com/white-paper/9117/en/" but this is only a SPI I need to maintain SCLK (Digital IO) in order to read from the Analogue port (Synchronize) X number of sample.

I am not sure if I should have one SCLK vi (starting by global definition) or have two interface assessing the same SCLK IO?  

The Hardware: is a NI5751 terminal.

Thanks