Termination of PCIe-6536 Output Clock

I have a clock signal coming from the PCIe-6536, going through an NI-Cable, and then into another of system module. This output signal is going into a high-impedance buffer, and the PCIe-6536 specification sheet notes that it should have a 50-Ohm output impedance with a maximum DC current drive of 16mA for 2.5V and 32mA for 3.3V. 

Should I assume that this is either a 50-Ohm characteristic impedance of the connector on the PCIe-6536 or that there is a 50-Ohm source impedance termination resistor? I cannot see how this would be a 50-Ohm parallel termination resistor at the transmitter of the PCIe-6536. If it is one of the first two options, clarification on which best describes the output structure would be appreciated. 

The main issue is that there are some anomalies noted in a subset of systems using the PCIe-6536 when there is no parallel termination at the input to the aforementioned high-impedance buffer in our other module. The anomalies are absent when a 50-ohm parallel termination (jumper option in current system) is present at the input to the buffer, but I would not want to use this for production as it would violate the maximum drive strength spec. Based on a collection of topics/pages for Generation Termination of the NI 654x, NI 655x, and NI656x, it appears that a 150-Ohm for 3.3V or 200-Ohm for 2.5V parallel termination might be feasible to not draw more current than the maximum rated for the output while also reducing potential reflections. 

An older version of this same system used a PCIe-6533 where 50-Ohm parallel terminations were used at the input to the high-impedance buffer (50-Ohm seems like it could be low due to drive current limit, but that is for past systems). During the migration to the PCIe-6536 from the PCIe-6533, someone noted that there were already termination resistors in the PCIe-6536. This resulted in the removal of the parallel termination resistors at the input to the buffer. I suspect that this may have been an error in the interpretation of the PCIe-6536 specification, but I would like to confirm with the community/NI support group before adding 150-Ohm parallel terminations into the system.

Does the community see any downsides to adding this parallel termination at the input to the aforementioned buffer when using the PCIe-6536, and is the output impedance specification meant as a series termination/characteristic impedance vs a parallel termination?

Thank you